loop counter
英 [luːp ˈkaʊntə(r)]
美 [luːp ˈkaʊntər]
网络 循环计数器; 计数器; 回圈计数器
双语例句
- Finally, the loop counter ($ I) is incremented, and the loop continues.
最后，循环计数器（$i）增加，循环继续。 - The load/ store instructions and the loop counter were geared for processing a single byte at a time.
load/store指令和循环计数器的目标是一次处理一个字节。 - Normally, variables are best named by their use ( like firstName or title), but as this variable is essentially a loop counter, using single letters is also fine.
变量一般最好根据用途命名（如firstName或rtitle），不过由于这个变量基本上是一个循环计数器，也可使用单个字母。 - Although MATLAB does allow you to use a variable of the same name as the loop counter within a loop, this is not a recommended practice.
循环变量只能作为右值（即可读不可写），当然你还可以在循环中使用一个名称和循环变量一样的变量，但是这种做法并不提倡。 - FPGA; DPLL ( Digital Phase-locked Loop); K-modulus counter; Intelligent modulus controller;
FPGA；数字锁相环；K模计数器；智能模值控制； - Code that changes the loop counter in the body of the loop is confusing and error prone.
在循环体中改变循环计数器的代码会让人感到迷惑，也容易犯错。 - The loop that does the reverse comparisons must have a loop counter and this loop counter produces the descending shift value that can be used to perform the BAD CHARACTER shift.
进行逆序比较的循环必须有一个计数器，这个计数器产生用于“不匹配字符”的移动的递减的位移值。 - Study on design method of engineer for current loop with counter electromotive force action
反电动势作用时电流闭环的工程设计方法研究 - Following the problem with the digital controller of the underground loop of the works 'imported Φ 114mm welded-pipe line that counting deviation occurred in the reciprocating vibration of the strip, the author analyses working theory of the said counter.
针对该厂引进的Φ114mm焊管生产线地下活套在带钢往复振荡运行中，数字控制器发生计数偏差问题，分析了计数器的工作原理。 - On the Determination of Boundary Value of Loop Counter
循环计数器边界值的正确设定 - This paper introduces the structure, functions, and features of CLC ( Cable Loop& Axle Counter) system, which is designed for increasing the stability of automatic block in low ballast resistance zone.
简要介绍解决低道床漏泄电阻区段自动闭塞稳定运用的CLC（计轴+环线）系统的主要设备构成、功能及特点。 - Modification of underground loop reversible counter
地下活套可逆计数器的改进 - Design of low power all digital phase-locked loop based on double edge triggered counter
基于双边沿触发计数器的低功耗全数字锁相环的设计 - The core frequency can be frequency-doubled to hundreds of megabytes with utilizing the advantages of integrating phase-locked loop of inner FPGA. A high frequency pulse counter has been designed and the stable pulsed drive scanning motor can be produced by use of frequency splitting of FPGA.
利用FPGA内部集成锁相环，核心频率可以倍频至几百兆的优点，设计了高频脉冲计数器并利用FPGA分频产生稳定的脉冲驱动扫描电机。 - In addition, the buffer, delay-locked loop and counter is designed to enlarge the measurement range.
并设计了缓冲器，延时锁相环，计数器来扩大测量范围。